1. Field of the Invention
The present invention relates to an even-number-stage pulse delay device including a ring delay line constituted of an even number of inverter circuits connected in a ring, and configured to cause a pulse edge to circulate around the ring delay line.
2. Description of Related Art
There is known a pulse phase difference encoding circuit provided with an even-number-stage pulse delay device for detecting a phase difference between two pulses and encoding the phase difference into a binary digital signal. For example, refer to Japanese Patent Application Laid-open No. 6-216721, or 7-183800.
This even-number-stage pulse delay device includes a ring delay line constituted of an even number of inverter circuits connected in a ring, each of the inverter circuits inverting an input signal passing therethrough. The ring delay line is configured such that one of the inverter circuits serves as a first starting inverter circuit which starts its inverting operation in response to a first control signal, and one of the inverter circuits excluding the first starting inverter circuit and the inverter circuit following this first starting inverter circuit serves as a second starting inverter circuit which starts its inverting operate in response to a second control signal.
This even-number-stage pulse delay device further includes a second-control-signal inputting circuit which inputs the second control signal to the second starting inverter circuit during a period from when the first starting inverter circuit starts its inverting operation in response to the first control signal inputted thereto to when an edge (main edge) of a pulse generated for the first time by the inverting operation reaches the second starting inverter circuit, by for example, inputting the output of one of the inverter circuit disposed between the first and second starting inverter circuits to the second starting inverter circuit as the second control signal.
That is, the second-control-signal inputting circuit causes the main edge and a reset edge of a pulse inverting oppositely to the main edge to circulate within the ring delay line.
According to the above even-number-stage pulse delay device, since the main edge and the reset edge circulates around the ring delay line keeping a predetermined distance (a predetermined number of the inverter gates) therebetween, it is possible to stably obtain an oscillation signal having a period determined by the number of the inverter circuits constituting the ring delay line.
Further, the pulse phase difference encoding circuit including the even-number-stage pulse delay device can easily encode the number of times that the main edge (or the reset edge) has circulated around the ring delay line and the position of the main edge (or the reset if the number of the inverter circuits constituting the ring delay line is set to 2n (n being a positive integer).
However, the above even-number-stage pulse delay device has a problem in that if one of the inverter circuits malfunctions due to external noise, for example, the circulation of the edge (pulse) is stopped because the ring delay line enters a stable state in which the outputs of each adjacent inverter circuits are at opposite levels.
Meanwhile, since the even-number-stage pulse delay device can be constituted of logic gate circuits such as inverter gate circuits, NAND gate circuits, or NOR gate circuits, the even-number-stage pulse delay device has been increasingly downsized and become faster with the miniaturization progress in semiconductor circuit manufacturing technique (process technique) like other digital circuits.
However, to make the even-number-stage pulse delay device compact in size and able to operate in high speed utilizing the miniaturization progress in semiconductor circuit manufacturing technique, it is necessary to lower the power supply voltage applied to the even-number-stage pulse delay device, although the noise immunity of the even-number-stage pulse delay device is degraded. Accordingly, in this case, when a large noise signal comes from outside, or when there occurs an abnormal momentary voltage drop, the circulation of the pulse within the ring delay line easily stops.
In addition, if the structure of the even-number-stage pulse delay device is modified to have multiple different transistor thresholds with the miniaturization progress in semiconductor circuit manufacturing technique, since the design margin of the even-number-stage pulse delay device is reduced, and manufacturing variation in electrical characteristics increases, it becomes difficult for the even-number-stage pulse delay device to operate stably.
It may occur that the circulation of the pulse within the ring delay line is forcibly stopped and restarted periodically for the even-number-stage pulse delay device to operate stably. However, this involves a problem that since the forcible stop and restart are performed even when the ring delay line is operating normally, needless dysfunctional periods occur, and electric power is consumed uselessly. Furthermore, since the even-number-stage pulse delay device has to be provided with a control circuit dedicated to perform the forcible stop and restart, the manufacturing cost increases.